show diagnostic result module all
show diagnostic result module all
import requests
import json
"""
Modify these please
"""
url='http://<ip_address>:<port_number>/ins'
switchuser='<user_id>'
switchpassword='<password>'
myheaders={'content-type':'application/json'}
payload={
"ins_api":{
"version": "1.0",
"type": "cli_show",
"chunk": "0",
"sid": "1",
"input": "show diagnostic result module all",
"output_format": "json"
}
}
response = requests.post(url,data=json.dumps(payload), headers=myheaders,auth=(switchuser,switchpassword)).json()
output = json.dumps(response, indent=4, sort_keys=True)
json_output = json.loads(output)["ins_api"]["outputs"]["output"]["body"]
print(json.dumps(json_output, indent=4, sort_keys=True))
{
"TABLE_Module": {
"ROW_Module": [
{
"TABLE_Test": {
"ROW_Test": [
{
"test_id": 1,
"testname": "ASICRegisterCheck",
"testresult": "Pass"
},
{
"test_id": 2,
"testname": "PrimaryBootROM",
"testresult": "Pass"
},
{
"test_id": 3,
"testname": "SecondaryBootROM",
"testresult": "Pass"
},
{
"test_id": 4,
"testname": "EOBCPortLoopback",
"testresult": "Pass"
},
{
"test_id": 5,
"testname": "OBFL",
"testresult": "Pass"
},
{
"aborted_ports": "none",
"err_disabled_ports": "none",
"failed_ports": "none",
"incomplete_ports": "none",
"passed_ports": "none",
"test_id": 6,
"testname": "PortLoopback",
"untested_ports": "1-48"
},
{
"aborted_ports": "none",
"err_disabled_ports": "none",
"failed_ports": "none",
"incomplete_ports": "none",
"passed_ports": "1-48",
"test_id": 7,
"testname": "SnakeLoopback",
"untested_ports": "none"
},
{
"aborted_ports": "none",
"err_disabled_ports": "none",
"failed_ports": "none",
"incomplete_ports": "none",
"passed_ports": "1-48",
"test_id": 8,
"testname": "IntPortLoopback",
"untested_ports": "none"
},
{
"aborted_ports": "none",
"err_disabled_ports": "none",
"failed_ports": "none",
"incomplete_ports": "none",
"passed_ports": "1",
"test_id": 9,
"testname": "RewriteEngineLoopback",
"untested_ports": "2-48"
},
{
"aborted_ports": "none",
"err_disabled_ports": "none",
"failed_ports": "none",
"incomplete_ports": "none",
"passed_ports": "none",
"test_id": 10,
"testname": "ExtPortLoopback",
"untested_ports": "1-48"
},
{
"aborted_ports": "none",
"err_disabled_ports": "none",
"failed_ports": "none",
"incomplete_ports": "none",
"passed_ports": "1-48",
"test_id": 11,
"testname": "BootupPortLoopback",
"untested_ports": "none"
}
]
},
"curr_diag_level": "complete",
"module_id": 2,
"module_name": "2/4/8/10/16 Gbps Advanced FC Module "
},
{
"TABLE_Test": {
"ROW_Test": [
{
"test_id": 1,
"testname": "ASICRegisterCheck",
"testresult": "Pass"
},
{
"test_id": 2,
"testname": "USB",
"testresult": "Pass"
},
{
"test_id": 3,
"testname": "NVRAM",
"testresult": "Pass"
},
{
"test_id": 4,
"testname": "RealTimeClock",
"testresult": "Pass"
},
{
"test_id": 5,
"testname": "PrimaryBootROM",
"testresult": "Pass"
},
{
"test_id": 6,
"testname": "SecondaryBootROM",
"testresult": "Pass"
},
{
"test_id": 7,
"testname": "CompactFlash",
"testresult": "Pass"
},
{
"test_id": 8,
"testname": "ExternalCompactFlash",
"testresult": "Pass"
},
{
"test_id": 9,
"testname": "PwrMgmtBus",
"testresult": "Pass"
},
{
"test_id": 10,
"testname": "SystemMgmtBus",
"testresult": "Untested"
},
{
"test_id": 11,
"testname": "StatusBus",
"testresult": "Untested"
},
{
"test_id": 12,
"testname": "PCIeBus",
"testresult": "Pass"
},
{
"test_id": 13,
"testname": "StandbyFabricLoopback",
"testresult": "Pass"
},
{
"test_id": 14,
"testname": "ManagementPortLoopback",
"testresult": "Pass"
},
{
"test_id": 15,
"testname": "EOBCPortLoopback",
"testresult": "Pass"
},
{
"test_id": 16,
"testname": "OBFL",
"testresult": "Pass"
}
]
},
"curr_diag_level": "complete",
"module_id": 3,
"module_name": "Supervisor Module-3 (Standby)"
},
{
"TABLE_Test": {
"ROW_Test": [
{
"test_id": 1,
"testname": "ASICRegisterCheck",
"testresult": "Pass"
},
{
"test_id": 2,
"testname": "USB",
"testresult": "Pass"
},
{
"test_id": 3,
"testname": "NVRAM",
"testresult": "Pass"
},
{
"test_id": 4,
"testname": "RealTimeClock",
"testresult": "Pass"
},
{
"test_id": 5,
"testname": "PrimaryBootROM",
"testresult": "Pass"
},
{
"test_id": 6,
"testname": "SecondaryBootROM",
"testresult": "Pass"
},
{
"test_id": 7,
"testname": "CompactFlash",
"testresult": "Pass"
},
{
"test_id": 8,
"testname": "ExternalCompactFlash",
"testresult": "Pass"
},
{
"test_id": 9,
"testname": "PwrMgmtBus",
"testresult": "Pass"
},
{
"test_id": 10,
"testname": "SystemMgmtBus",
"testresult": "Pass"
},
{
"test_id": 11,
"testname": "StatusBus",
"testresult": "Pass"
},
{
"test_id": 12,
"testname": "PCIeBus",
"testresult": "Pass"
},
{
"test_id": 13,
"testname": "StandbyFabricLoopback",
"testresult": "Untested"
},
{
"test_id": 14,
"testname": "ManagementPortLoopback",
"testresult": "Pass"
},
{
"test_id": 15,
"testname": "EOBCPortLoopback",
"testresult": "Pass"
},
{
"test_id": 16,
"testname": "OBFL",
"testresult": "Pass"
}
]
},
"curr_diag_level": "complete",
"module_id": 4,
"module_name": "Supervisor Module-3 (Active)"
}
]
}
}
<TABLE_Module>
<ROW_Module>
<module_id>2</module_id>
<curr_diag_level>complete</curr_diag_level>
<module_name>2/4/8/10/16 Gbps Advanced FC Module </module_name>
<TABLE_Test>
<ROW_Test>
<test_id>1</test_id>
<testname>ASICRegisterCheck</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>2</test_id>
<testname>PrimaryBootROM</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>3</test_id>
<testname>SecondaryBootROM</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>4</test_id>
<testname>EOBCPortLoopback</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>5</test_id>
<testname>OBFL</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>6</test_id>
<testname>PortLoopback</testname>
<passed_ports>none</passed_ports>
<failed_ports>none</failed_ports>
<incomplete_ports>none</incomplete_ports>
<untested_ports>1-48</untested_ports>
<aborted_ports>none</aborted_ports>
<err_disabled_ports>none</err_disabled_ports>
</ROW_Test>
<ROW_Test>
<test_id>7</test_id>
<testname>SnakeLoopback</testname>
<passed_ports>1-48</passed_ports>
<failed_ports>none</failed_ports>
<incomplete_ports>none</incomplete_ports>
<untested_ports>none</untested_ports>
<aborted_ports>none</aborted_ports>
<err_disabled_ports>none</err_disabled_ports>
</ROW_Test>
<ROW_Test>
<test_id>8</test_id>
<testname>IntPortLoopback</testname>
<passed_ports>1-48</passed_ports>
<failed_ports>none</failed_ports>
<incomplete_ports>none</incomplete_ports>
<untested_ports>none</untested_ports>
<aborted_ports>none</aborted_ports>
<err_disabled_ports>none</err_disabled_ports>
</ROW_Test>
<ROW_Test>
<test_id>9</test_id>
<testname>RewriteEngineLoopback</testname>
<passed_ports>1</passed_ports>
<failed_ports>none</failed_ports>
<incomplete_ports>none</incomplete_ports>
<untested_ports>2-48</untested_ports>
<aborted_ports>none</aborted_ports>
<err_disabled_ports>none</err_disabled_ports>
</ROW_Test>
<ROW_Test>
<test_id>10</test_id>
<testname>ExtPortLoopback</testname>
<passed_ports>none</passed_ports>
<failed_ports>none</failed_ports>
<incomplete_ports>none</incomplete_ports>
<untested_ports>1-48</untested_ports>
<aborted_ports>none</aborted_ports>
<err_disabled_ports>none</err_disabled_ports>
</ROW_Test>
<ROW_Test>
<test_id>11</test_id>
<testname>BootupPortLoopback</testname>
<passed_ports>1-48</passed_ports>
<failed_ports>none</failed_ports>
<incomplete_ports>none</incomplete_ports>
<untested_ports>none</untested_ports>
<aborted_ports>none</aborted_ports>
<err_disabled_ports>none</err_disabled_ports>
</ROW_Test>
</TABLE_Test>
</ROW_Module>
<ROW_Module>
<module_id>3</module_id>
<curr_diag_level>complete</curr_diag_level>
<module_name>Supervisor Module-3 (Standby)</module_name>
<TABLE_Test>
<ROW_Test>
<test_id>1</test_id>
<testname>ASICRegisterCheck</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>2</test_id>
<testname>USB</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>3</test_id>
<testname>NVRAM</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>4</test_id>
<testname>RealTimeClock</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>5</test_id>
<testname>PrimaryBootROM</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>6</test_id>
<testname>SecondaryBootROM</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>7</test_id>
<testname>CompactFlash</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>8</test_id>
<testname>ExternalCompactFlash</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>9</test_id>
<testname>PwrMgmtBus</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>10</test_id>
<testname>SystemMgmtBus</testname>
<testresult>Untested</testresult>
</ROW_Test>
<ROW_Test>
<test_id>11</test_id>
<testname>StatusBus</testname>
<testresult>Untested</testresult>
</ROW_Test>
<ROW_Test>
<test_id>12</test_id>
<testname>PCIeBus</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>13</test_id>
<testname>StandbyFabricLoopback</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>14</test_id>
<testname>ManagementPortLoopback</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>15</test_id>
<testname>EOBCPortLoopback</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>16</test_id>
<testname>OBFL</testname>
<testresult>Pass</testresult>
</ROW_Test>
</TABLE_Test>
</ROW_Module>
<ROW_Module>
<module_id>4</module_id>
<curr_diag_level>complete</curr_diag_level>
<module_name>Supervisor Module-3 (Active)</module_name>
<TABLE_Test>
<ROW_Test>
<test_id>1</test_id>
<testname>ASICRegisterCheck</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>2</test_id>
<testname>USB</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>3</test_id>
<testname>NVRAM</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>4</test_id>
<testname>RealTimeClock</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>5</test_id>
<testname>PrimaryBootROM</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>6</test_id>
<testname>SecondaryBootROM</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>7</test_id>
<testname>CompactFlash</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>8</test_id>
<testname>ExternalCompactFlash</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>9</test_id>
<testname>PwrMgmtBus</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>10</test_id>
<testname>SystemMgmtBus</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>11</test_id>
<testname>StatusBus</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>12</test_id>
<testname>PCIeBus</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>13</test_id>
<testname>StandbyFabricLoopback</testname>
<testresult>Untested</testresult>
</ROW_Test>
<ROW_Test>
<test_id>14</test_id>
<testname>ManagementPortLoopback</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>15</test_id>
<testname>EOBCPortLoopback</testname>
<testresult>Pass</testresult>
</ROW_Test>
<ROW_Test>
<test_id>16</test_id>
<testname>OBFL</testname>
<testresult>Pass</testresult>
</ROW_Test>
</TABLE_Test>
</ROW_Module>
</TABLE_Module>
The show diagnostic result module all command displays the information about the diagnostic test result for all the test ID.
For command descriptions, see the Cisco MDS 9000 Series Switches Command References.
Note: This sample output is generated for Cisco MDS 9000 Series NX-OS Release 8.4(2a) or later.
| CLI Output |
|---|
|
| Parameter | Description | Type | Sample Values |
|---|---|---|---|
| testresult | Test results | String | ['. = Pass', ' F = Fail', ' I = Incomplete', ' U = Untested', ' A = Abort', ' E = Error disabled'] |
| curr_diag_level | Current diagonstic level | String | ['complete', 'bypass'] |
| testname | Test name | String | |
| module_name | Module name | String | |
| module_id | Module ID | Integer | |
| test_id | Test ID of tests | Integer | |
| incomplete_ports | List of incompletly tested ports | String | |
| aborted_ports | List of aborted ports | String | |
| failed_ports | List of failed ports | String | |
| err_disabled_ports | List of error disabled ports | String | |
| untested_ports | List of ignored test ports | String | |
| passed_ports | List of passed ports | String |