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PHY-MAC Interface There are three MAC-PHY interfaces to support different applications while optimizing a number of high speed SERDES between ASIC and PHYs. These interfaces provide headers to communicate control/data, auto-neg information between ASIC and PHY.

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Universal SGMII and Univerisal XGMII MAC-PHY Interface

Build next generation PHY and MACs with the ability to perform first auto-neg without PLL and SERDES parameters for 1G, 2.5G. 5G and 10G BASE-T Ethernet products.

USGMII and USXGMII Summary


USGMII Specification

The Universal Serial Gigabit Media Independent Interface (USGMII) is an extension of the current SGMII and QSGMII. USGMII provides flexibility to add new features while maintaining backward compatibility. Previous definition/implementations cover single (SGMII) and quad (QSGMII) options. This specification defines USGMII option to support 4x1GE/8 x1GE network ports and 5G/10G PHY/MAC SERDES interface speed respectively.

USXGMII - Single Network port over a Single SERDES

The Universal Serial Media Independent Interface for carrying SINGLE network ports over a single SERDES (USXGMII-M) for Multi-Gigabit technology at 10M/100M/1G/2.5G/5G/10G data rate and 5G/10G PHY/MAC interface SERDES data rate.

USXGMII - Multiple Network ports over a Single SERDES

The Universal Serial Media Independent Interface for carrying MULTIPLE network ports over a single SERDES (USXGMII-M) for Multi-Gigabit technology at 10M/100M/1G/2.5G/5G/10G data rate and 5G/10G PHY/MAC interface SERDES data rate.

Downloads


USGMII_Specification

 

USGMII_Specification.pdf

USXGMII_Singleport_Copper_Interface

 

USXGMII_Singleport_Copper_Interface.pdf

USXGMII_Multiport_Copper_Interface

 

USXGMII_Multiport_Copper_Interface.pdf