Diagnostic Commands - Cisco Nexus 9000 Series NX-API CLI, Release 9.3(x)

Cisco Nexus 9000 Series NX-API CLI, Release 9.3(x)

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Cisco Nexus 9000 Series NX-API CLI Reference, Release 9.3x

show diagnostic content module all

Python

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import json

"""
Modify these please
"""
url='http://<IP_Address>/ins'
switchuser='<User_ID>'
switchpassword='<Password>'

myheaders={'content-type':'application/json'}
payload={
  "ins_api":{
  "version": "1.0",
  "type": "cli_show",
  "chunk": "0",
  "sid": "1",
  "input": "show diagnostic content module all",
  "output_format": "json"
}

response = requests.post(url,data=json.dumps(payload), headers=myheaders,auth=(switchuser,switchpassword)).json()
output = json.dumps(response, indent=4, sort_keys=True)


{

  "ins_api": {
    "type": "cli_show",
    "version": "1.0",
    "sid": "eoc",
    "outputs": {
      "output": {
        "input": "show diagnostic content module all",
        "msg": "Success",
        "code": "200",
        "body": {
          "attr_descr": "Diagnostics test suite attributes: \nB/C/* - Bypass bootup level test / Complete bootup level test / NA \nP/*   - Per port test / NA \nM/S/* - Only applicable to active / standby unit / NA \nD/N/* - Disruptive test / Non-disruptive test / NA \nH/O/* - Always enabled monitoring test / Conditionally enabled test / NA \nF/*   - Fixed monitoring interval test / NA \nX/*   - Not a health monitoring test / NA \nE/*   - Sup to line card test / NA \nL/*   - Exclusively run this test / NA \nT/*   - Not an ondemand test / NA \nA/I/* - Monitoring is active / Monitoring is inactive / NA",
          "TABLE_Module": {
            "ROW_Module": {
              "module_id": "1",
              "module_type": "48x10GT + 6x40G/100G Ethernet Module (Active)",
              "TABLE_test": {
                "ROW_test": [
                  {
                    "test_id": "1",
                    "testname": "USB",
                    "test_attr": "C**N**X**T*",
                    "test_interval": "-NA-"
                  },
                  {
                    "test_id": "2",
                    "testname": "NVRAM",
                    "test_attr": "***N******A",
                    "test_interval": "00:05:00"
                  },
                  {
                    "test_id": "3",
                    "testname": "RealTimeClock",
                    "test_attr": "***N******A",
                    "test_interval": "00:05:00"
                  },
                  {
                    "test_id": "4",
                    "testname": "PrimaryBootROM",
                    "test_attr": "***N******A",
                    "test_interval": "00:30:00"
                  },
                  {
                    "test_id": "5",
                    "testname": "SecondaryBootROM",
                    "test_attr": "***N******A",
                    "test_interval": "00:30:00"
                  },
                  {
                    "test_id": "6",
                    "testname": "BootFlash",
                    "test_attr": "***N******A",
                    "test_interval": "00:30:00"
                  },
                  {
                    "test_id": "7",
                    "testname": "SystemMgmtBus",
                    "test_attr": "**MN******A",
                    "test_interval": "00:00:30"
                  },
                  {
                    "test_id": "8",
                    "testname": "OBFL",
                    "test_attr": "C**N**X**T*",
                    "test_interval": "-NA-"
                  },
                  {
                    "test_id": "9",
                    "testname": "ACT2",
                    "test_attr": "***N******A",
                    "test_interval": "00:30:00"
                  },
                  {
                    "test_id": "10",
                    "testname": "Console",
                    "test_attr": "***N******A",
                    "test_interval": "00:00:30"
                  },
                  {
                    "test_id": "11",
                    "testname": "FpgaRegTest",
                    "test_attr": "***N******A",
                    "test_interval": "00:00:30"
                  },
                  {
                    "test_id": "12",
                    "testname": "Mce",
                    "test_attr": "***N******A",
                    "test_interval": "01:00:00"
                  },
                  {
                    "test_id": "13",
                    "testname": "AsicMemory",
                    "test_attr": "C**D**X**T*",
                    "test_interval": "-NA-"
                  },
                  {
                    "test_id": "14",
                    "testname": "Pcie",
                    "test_attr": "C**N**X**T*",
                    "test_interval": "-NA-"
                  },
                  {
                    "test_id": "15",
                    "testname": "PortLoopback",
                    "test_attr": "*P*N**XE***",
                    "test_interval": "-NA-"
                  },
                  {
                    "test_id": "16",
                    "testname": "L2ACLRedirect",
                    "test_attr": "*P*N***E**A",
                    "test_interval": "00:01:00"
                  },
                  {
                    "test_id": "17",
                    "testname": "BootupPortLoopback",
                    "test_attr": "CP*N**XE*T*",
                    "test_interval": "-NA-"
                  }
                ]
              }
            }
          }
        }
      }
    }
  }
}

show diagnostic content module all

The CLI output example below corresponds to the payload example in the code pane on the right. For more information about the show diagnostic content module all command, see the CLI command reference:

http://www.cisco.com/c/en/us/support/switches/nexus-9000-series-switches/products-command-reference-list.html

Note: This example was added in Cisco NX-OS Release 9.2(1).

CLI Output

CLI Output
Switch# show diagnostic content module all Diagnostics test suite attributes: B/C/ - Bypass bootup level test / Complete bootup level test / NA P/ - Per port test / NA M/S/ - Only applicable to active / standby unit / NA D/N/ - Disruptive test / Non-disruptive test / NA H/O/ - Always enabled monitoring test / Conditionally enabled test / NA F/ - Fixed monitoring interval test / NA X/ - Not a health monitoring test / NA E/ - Sup to line card test / NA L/ - Exclusively run this test / NA T/ - Not an ondemand test / NA A/I/ - Monitoring is active / Monitoring is inactive / NA Module 1: 48x10GT + 6x40G/100G Ethernet Module (Active) Testing Interval ID Name Attributes (hh:mm:ss) __ __ _ 1) USB---------------------------> CNX*T -NA- 2) NVRAM-------------------------> NA 00:05:00 3) RealTimeClock-----------------> NA 00:05:00 4) PrimaryBootROM----------------> NA 00:30:00 5) SecondaryBootROM--------------> NA 00:30:00 6) BootFlash---------------------> NA 00:30:00 7) SystemMgmtBus-----------------> MNA 00:00:30 8) OBFL--------------------------> CNXT -NA- 9) ACT2--------------------------> NA 00:30:00 10) Console-----------------------> NA 00:00:30 11) FpgaRegTest-------------------> NA 00:00:30 12) Mce---------------------------> NA 01:00:00 13) AsicMemory--------------------> CDXT -NA- 14) Pcie--------------------------> CNXT -NA- 15) PortLoopback------------------> PNXE -NA- 16) L2ACLRedirect-----------------> PNEA 00:01:00 17) BootupPortLoopback------------> CPNXET -NA-

Switch# show diagnostic content module all
Diagnostics test suite attributes: 
B/C/ - Bypass bootup level test / Complete bootup level test / NA 
P/   - Per port test / NA 
M/S/ - Only applicable to active / standby unit / NA 
D/N/ - Disruptive test / Non-disruptive test / NA 
H/O/ - Always enabled monitoring test / Conditionally enabled test / NA 
F/   - Fixed monitoring interval test / NA 
X/   - Not a health monitoring test / NA 
E/   - Sup to line card test / NA 
L/   - Exclusively run this test / NA 
T/   - Not an ondemand test / NA 
A/I/ - Monitoring is active / Monitoring is inactive / NA


Module 1: 48x10GT + 6x40G/100G Ethernet Module (Active) 

                                                       Testing Interval
ID     Name                               Attributes      (hh:mm:ss) 
   __ __   _ 
 1)    USB--------------------------->     CNX**T     -NA-
 2)    NVRAM------------------------->     N*A     00:05:00
 3)    RealTimeClock----------------->     N*A     00:05:00
 4)    PrimaryBootROM---------------->     N*A     00:30:00
 5)    SecondaryBootROM-------------->     N*A     00:30:00
 6)    BootFlash--------------------->     N*A     00:30:00
 7)    SystemMgmtBus----------------->     MN**A     00:00:30
 8)    OBFL-------------------------->     CNXT     -NA-
 9)    ACT2-------------------------->     N**A     00:30:00
10)    Console----------------------->     N*A     00:00:30
11)    FpgaRegTest------------------->     N*A     00:00:30
12)    Mce--------------------------->     N*A     01:00:00
13)    AsicMemory-------------------->     CDXT*     -NA-
14)    Pcie-------------------------->     CNXT     -NA-
15)    PortLoopback------------------>     PNXE     -NA-
16)    L2ACLRedirect----------------->     PN*EA     00:01:00
17)    BootupPortLoopback------------>     CPN**XET*     -NA-

show diagnostic result module all

The CLI output example below corresponds to the payload example in the code pane on the right. For more information about the show diagnostic result module all command, see the CLI command reference:

http://www.cisco.com/c/en/us/support/switches/nexus-9000-series-switches/products-command-reference-list.html

Note: This example was added in Cisco NX-OS Release 9.2(1).

CLI Output

CLI Output
Switch# show diagnostic result module all Current bootup diagnostic level: complete Module 1: 48x10GT + 6x40G/100G Ethernet Module (Active) Test results: (. = Pass, F = Fail, I = Incomplete, U = Untested, A = Abort, E = Error disabled) 1) USB---------------------------> . 2) NVRAM-------------------------> . 3) RealTimeClock-----------------> . 4) PrimaryBootROM----------------> . 5) SecondaryBootROM--------------> . 6) BootFlash---------------------> . 7) SystemMgmtBus-----------------> . 8) OBFL--------------------------> . 9) ACT2--------------------------> . 10) Console-----------------------> . 11) FpgaRegTest-------------------> . 12) Mce---------------------------> . 13) AsicMemory--------------------> . 14) Pcie--------------------------> . 15) PortLoopback: U Port 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 ------------------------------------------------------------------ U U U U U U U U U U U U U U U U Port 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 209 210 211 212 213 214 215 216 ------------------------------------- U U U U U U U U 16) L2ACLRedirect-----------------> . 17) BootupPortLoopback: . Port 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 ------------------------------------------------------------------ . U U U . U U U . U U U . U U U Port 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 209 210 211 212 213 214 215 216 ------------------------------------- U U U U U U U U

Switch# show diagnostic result module all 

Current bootup diagnostic level: complete
Module 1: 48x10GT + 6x40G/100G Ethernet Module  (Active)

    Test results: (. = Pass, F = Fail, I = Incomplete,
    U = Untested, A = Abort, E = Error disabled)

     1) USB---------------------------> .
     2) NVRAM-------------------------> .
     3) RealTimeClock-----------------> .
     4) PrimaryBootROM----------------> .
     5) SecondaryBootROM--------------> .
     6) BootFlash---------------------> .
     7) SystemMgmtBus-----------------> .
     8) OBFL--------------------------> .
     9) ACT2--------------------------> .
    10) Console-----------------------> .
    11) FpgaRegTest-------------------> .
    12) Mce---------------------------> .
    13) AsicMemory--------------------> .
    14) Pcie--------------------------> .
    15) PortLoopback: U 

      Port      1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 
      ------------------------------------------------------------------
             U  U  U  U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     209 210 211 212 213 214 215 216 
      -------------------------------------
             U   U   U   U   U   U   U   U


    16) L2ACLRedirect-----------------> .
    17) BootupPortLoopback: . 

      Port      1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 
      ------------------------------------------------------------------
             .  U  U  U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     209 210 211 212 213 214 215 216 
      -------------------------------------
             U   U   U   U   U   U   U   U

show diagnostic result module all detail

The CLI output example below corresponds to the payload example in the code pane on the right. For more information about the show diagnostic result module all detail command, see the CLI command reference:

http://www.cisco.com/c/en/us/support/switches/nexus-9000-series-switches/products-command-reference-list.html

Note: This example was added in Cisco NX-OS Release 9.2(1).

CLI Output

CLI Output
Switch# show diagnostic result module all detail Current bootup diagnostic level: complete Module 1: 48x10GT + 6x40G/100G Ethernet Module (Active) Diagnostic level at card bootup: complete Test results: (. = Pass, F = Fail, I = Incomplete, U = Untested, A = Abort, E = Error disabled) __ 1) USB . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 1 Last test execution time ----> Wed Aug 29 21:10:47 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Wed Aug 29 21:10:47 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> n/a __ 2) NVRAM . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 249 Last test execution time ----> Thu Aug 30 17:51:27 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:51:27 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 17:56:27 2018 __ 3) RealTimeClock . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 249 Last test execution time ----> Thu Aug 30 17:51:27 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:51:31 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 17:56:31 2018 __ 4) PrimaryBootROM . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 42 Last test execution time ----> Thu Aug 30 17:41:26 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:41:35 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 18:11:35 2018 __ 5) SecondaryBootROM . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 42 Last test execution time ----> Thu Aug 30 17:41:26 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:41:45 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 18:11:45 2018 __ 6) BootFlash . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 42 Last test execution time ----> Thu Aug 30 17:41:26 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:41:46 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 18:11:46 2018 __ 7) SystemMgmtBus . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 2485 Last test execution time ----> Thu Aug 30 17:53:38 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:53:38 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 17:54:08 2018 Chassis Fan 1 2 3 4 --------------------------------------------------------------------- . . . . PS 1 2 --------------------------------------------------------------------- . . __ 8) OBFL . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 1 Last test execution time ----> Wed Aug 29 21:10:47 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Wed Aug 29 21:10:47 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> n/a __ 9) ACT2 . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 42 Last test execution time ----> Thu Aug 30 17:41:26 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:41:46 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 18:11:46 2018 __ 10) Console . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 2485 Last test execution time ----> Thu Aug 30 17:53:38 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:53:38 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 17:54:08 2018 __ 11) FpgaRegTest . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 2485 Last test execution time ----> Thu Aug 30 17:53:38 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:53:38 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 17:54:08 2018 __ 12) Mce . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 21 Last test execution time ----> Thu Aug 30 17:11:26 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:11:45 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 18:11:45 2018 __ 13) AsicMemory . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 1 Last test execution time ----> Wed Aug 29 21:11:17 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Wed Aug 29 21:11:17 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> n/a SUG 1 --------------------------------------------------------------------- . __ 14) Pcie . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 1 Last test execution time ----> Wed Aug 29 21:11:17 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Wed Aug 29 21:11:17 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> n/a __ 15) PortLoopback: U Port 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 ----------------------------------------------------- U U U U U U U U U U U U U U U U Port 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 ------------------------------------------------------------------ U U U U U U U U U U U U U U U U Port 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 209 210 211 212 213 214 215 216 ------------------------------------- U U U U U U U U Error code ------------------> DIAG TEST UNTESTED(SUCCESS) Total run count -------------> 0 Last test execution time ----> n/a First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> n/a Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> n/a __ 16) L2ACLRedirect . Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 1243 Last test execution time ----> Thu Aug 30 17:53:33 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Thu Aug 30 17:53:33 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> Thu Aug 30 17:54:33 2018 SUG 1 --------------------------------------------------------------------- . __ 17) BootupPortLoopback: . Port 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 ----------------------------------------------------- . U U U . U U U . U U U . U U U Port 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 ------------------------------------------------------------------ . U U U . U U U . U U U . U U U Port 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 --------------------------------------------------------------------- . U U U . U U U . U U U . U U U Port 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 --------------------------------------------------------------------- U U U U U U U U U U U U U U U U Port 209 210 211 212 213 214 215 216 ------------------------------------- U U U U U U U U Error code ------------------> DIAG TEST SUCCESS Total run count -------------> 1 Last test execution time ----> Wed Aug 29 21:11:22 2018 First test failure time -----> n/a Last test failure time ------> n/a Last test pass time ---------> Wed Aug 29 21:11:25 2018 Total failure count ---------> 0 Consecutive failure count ---> 0 Last failure reason ---------> No failures yet Next Execution time ---------> n/a __

Switch# show diagnostic result module all detail

Current bootup diagnostic level: complete
Module 1: 48x10GT + 6x40G/100G Ethernet Module  (Active)

  Diagnostic level at card bootup: complete

    Test results: (. = Pass, F = Fail, I = Incomplete,
    U = Untested, A = Abort, E = Error disabled)

    __

    1) USB .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 1
        Last test execution time ----> Wed Aug 29 21:10:47 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Wed Aug 29 21:10:47 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time --------->  n/a
    __

    2) NVRAM .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 249
        Last test execution time ----> Thu Aug 30 17:51:27 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:51:27 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 17:56:27 2018
    __

    3) RealTimeClock .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 249
        Last test execution time ----> Thu Aug 30 17:51:27 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:51:31 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 17:56:31 2018
    __

    4) PrimaryBootROM .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 42
        Last test execution time ----> Thu Aug 30 17:41:26 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:41:35 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 18:11:35 2018
    __

    5) SecondaryBootROM .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 42
        Last test execution time ----> Thu Aug 30 17:41:26 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:41:45 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 18:11:45 2018
    __

    6) BootFlash .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 42
        Last test execution time ----> Thu Aug 30 17:41:26 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:41:46 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 18:11:46 2018
    __

    7) SystemMgmtBus .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 2485
        Last test execution time ----> Thu Aug 30 17:53:38 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:53:38 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 17:54:08 2018

    Chassis Fan       1  2  3  4
         ---------------------------------------------------------------------
              .  .  .  .
    PS            1  2
         ---------------------------------------------------------------------
              .  .

    __

    8) OBFL .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 1
        Last test execution time ----> Wed Aug 29 21:10:47 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Wed Aug 29 21:10:47 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time --------->  n/a
    __

    9) ACT2 .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 42
        Last test execution time ----> Thu Aug 30 17:41:26 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:41:46 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 18:11:46 2018
    __

    10) Console .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 2485
        Last test execution time ----> Thu Aug 30 17:53:38 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:53:38 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 17:54:08 2018
    __

    11) FpgaRegTest .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 2485
        Last test execution time ----> Thu Aug 30 17:53:38 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:53:38 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 17:54:08 2018
    __

    12) Mce .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 21
        Last test execution time ----> Thu Aug 30 17:11:26 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:11:45 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 18:11:45 2018
    __

    13) AsicMemory .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 1
        Last test execution time ----> Wed Aug 29 21:11:17 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Wed Aug 29 21:11:17 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time --------->  n/a

     SUG          1
         ---------------------------------------------------------------------
               .

    __

    14) Pcie .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 1
        Last test execution time ----> Wed Aug 29 21:11:17 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Wed Aug 29 21:11:17 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time --------->  n/a
    __

    15) PortLoopback: U 

      Port      1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 
      -----------------------------------------------------
             U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

      Port     97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 
      ------------------------------------------------------------------
             U  U  U  U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     209 210 211 212 213 214 215 216 
      -------------------------------------
             U   U   U   U   U   U   U   U


        Error code ------------------> DIAG TEST UNTESTED(SUCCESS)
        Total run count -------------> 0
        Last test execution time ---->  n/a
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time --------->  n/a
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time --------->  n/a
    __

    16) L2ACLRedirect .

        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 1243
        Last test execution time ----> Thu Aug 30 17:53:33 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Thu Aug 30 17:53:33 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time ---------> Thu Aug 30 17:54:33 2018

     SUG          1
         ---------------------------------------------------------------------
               .

    __

    17) BootupPortLoopback: . 

      Port      1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 
      -----------------------------------------------------
             .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

      Port     97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 
      ------------------------------------------------------------------
             .  U  U  U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 
      ---------------------------------------------------------------------
             .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U

      Port     193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 
      ---------------------------------------------------------------------
             U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U

      Port     209 210 211 212 213 214 215 216 
      -------------------------------------
             U   U   U   U   U   U   U   U


        Error code ------------------> DIAG TEST SUCCESS
        Total run count -------------> 1
        Last test execution time ----> Wed Aug 29 21:11:22 2018
        First test failure time ----->  n/a
        Last test failure time ------>  n/a
        Last test pass time ---------> Wed Aug 29 21:11:25 2018
        Total failure count ---------> 0
        Consecutive failure count ---> 0
        Last failure reason ---------> No failures yet
        Next Execution time --------->  n/a
    __