show diagnostic result module 1

show diagnostic result module 1

import json

"""
Modify these please
"""
url='http://<IP_Address>/ins'
switchuser='<User_ID>'
switchpassword='<Password>'

myheaders={'content-type':'application/json'}
payload={
  "ins_api":{
  "version": "1.0",
  "type": "cli_show",
  "chunk": "0",
  "sid": "1",
  "input": "show diagnostic result module 1",
  "output_format": "json"
}

response = requests.post(url,data=json.dumps(payload), headers=myheaders,auth=(switchuser,switchpassword)).json()
output = json.dumps(response, indent=4, sort_keys=True)


{

    "ins_api": {
        "outputs": {
            "output": {
                "body": {
                    "TABLE_Test": {
                        "ROW_Test": [
                            {
                                "test_id": 1, 
                                "testname": "ASICRegisterCheck", 
                                "testresult": "Pass"
                            }, 
                            {
                                "test_id": 2, 
                                "testname": "PrimaryBootROM", 
                                "testresult": "Pass"
                            }, 
                            {
                                "test_id": 3, 
                                "testname": "SecondaryBootROM", 
                                "testresult": "Pass"
                            }, 
                            {
                                "test_id": 4, 
                                "testname": "OBFL", 
                                "testresult": "Pass"
                            }, 
                            {
                                "test_id": 5, 
                                "testname": "ACT2", 
                                "testresult": "Pass"
                            }, 
                            {
                                "test_id": 6, 
                                "testname": "BootFlash", 
                                "testresult": "Untested"
                            }, 
                            {
                                "test_id": 7, 
                                "testname": "AsicMemory", 
                                "testresult": "Pass"
                            }, 
                            {
                                "test_id": 8, 
                                "testname": "FpgaRegTest", 
                                "testresult": "Pass"
                            }, 
                            {
                                "test_id": 9, 
                                "testname": "Pcie", 
                                "testresult": "Pass"
                            }, 
                            {
                                "aborted_ports": "none", 
                                "err_disabled_ports": "none", 
                                "failed_ports": "none", 
                                "incomplete_ports": "none", 
                                "passed_ports": "none", 
                                "test_id": 10, 
                                "testname": "PortLoopback", 
                                "testresult": "Untested", 
                                "untested_ports": "1-128"
                            }, 
                            {
                                "test_id": 11, 
                                "testname": "L2ACLRedirect", 
                                "testresult": "Pass"
                            }, 
                            {
                                "aborted_ports": "none", 
                                "err_disabled_ports": "none", 
                                "failed_ports": "none", 
                                "incomplete_ports": "none", 
                                "passed_ports": "1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,61,65,69,73,77,81,85,89,93,97,101,105,109,113,117,121,125", 
                                "test_id": 12, 
                                "testname": "BootupPortLoopback", 
                                "testresult": "Pass", 
                                "untested_ports": "2-4,6-8,10-12,14-16,18-20,22-24,26-28,30-32,34-36,38-40,42-44,46-48,50-52,54-56,58-60,62-64,66-68,70-72,74-76,78-80,82-84,86-88,90-92,94-96,98-100,102-104,106-108,110-112,114-116,118-120,122-124,126-128"
                            }
                        ]
                    }, 
                    "curr_diag_level": "complete", 
                    "module_id": 1, 
                    "module_name": "32x100G Ethernet Module "
                }, 
                "code": "200", 
                "input": "show diagnostic result module 1", 
                "msg": "Success"
            }
        }, 
        "sid": "eoc", 
        "type": "cli_show", 
        "version": "1.0"
    }
}

The CLI output example below corresponds to the payload example in the code pane on the right. For more information about the show diagnostic result module 1 command, see the CLI command reference:

http://www.cisco.com/c/en/us/support/switches/nexus-9000-series-switches/products-command-reference-list.html

Note: This example was added in Cisco NX-OS Release 7.0(3)I7(4).

Switch# show diagnostic result module 1

Current bootup diagnostic level: complete
Module 1: 32x100G Ethernet Module

 Test results: (. = Pass, F = Fail, I = Incomplete,
 U = Untested, A = Abort, E = Error disabled)

  1) ASICRegisterCheck-------------  .
  2) PrimaryBootROM----------------  .
  3) SecondaryBootROM--------------  .
  4) OBFL--------------------------  .
  5) ACT2--------------------------  .
  6) BootFlash---------------------  U
  7) AsicMemory--------------------  .
  8) FpgaRegTest-------------------  .
  9) Pcie--------------------------  .
 10) PortLoopback: U 

   Port   1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 
   -----------------------------------------------------
          U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

   Port  17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 
   -----------------------------------------------------
          U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

   Port  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 
   -----------------------------------------------------
          U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

   Port  49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 
   -----------------------------------------------------
          U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

   Port  65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 
   -----------------------------------------------------
          U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

   Port  81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 
   -----------------------------------------------------
          U  U  U  U  U  U  U  U  U  U  U  U  U  U  U  U

   Port  97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 
   ------------------------------------------------------------------
          U  U  U  U   U   U   U   U   U   U   U   U   U   U   U   U

   Port  113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 
   ---------------------------------------------------------------------
          U   U   U   U   U   U   U   U   U   U   U   U   U   U   U   U


 11) L2ACLRedirect-----------------  .
 12) BootupPortLoopback: . 

   Port   1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 
   -----------------------------------------------------
          .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

   Port  17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 
   -----------------------------------------------------
          .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

   Port  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 
   -----------------------------------------------------
          .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

   Port  49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 
   -----------------------------------------------------
          .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

   Port  65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 
   -----------------------------------------------------
          .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

   Port  81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 
   -----------------------------------------------------
          .  U  U  U  .  U  U  U  .  U  U  U  .  U  U  U

   Port  97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 
   ------------------------------------------------------------------
          .  U  U  U   .   U   U   U   .   U   U   U   .   U   U   U

   Port  113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 
   ---------------------------------------------------------------------
          .   U   U   U   .   U   U   U   .   U   U   U   .   U   U   U